Modern sub-threshold SoC designs feature multiple power domains to dynamically track the maximum energy efficiency point (62 mV to 0.45V) in response to application demands. The following publications concern such designs.    Y. Okuma et al., “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS,” CICC., 2010.    A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State 748 Circuits, vol. 40, no. 1, pp. 310-319, January 2005.    B. H. Calhoun and A. P. Chandrakasan, “Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238-245, January 2006.    H. Kaul et al., “A 320 mV 56 μW 411 GOPS/Watt ultra-low voltage motion estimation accelerator in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, February 2008, pp. 316-616.    J. Kwong, Y. K Ramadass, N. Verma, and A. P. Chandrakasan, “A 65 nm sub-Vt microcontroller with integrated SRAM and switched capacitor DC-DC converter,” IEEE J. Solid-State Circuits, vol. 44, no. 1, 758 pp. 115-126, January 2009.    A. Agarwal et al., “A 320 mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, February 2010, pp. 328-329.    N. Lotze and Y. Manoli, “A 62 mV 0.13 μm CMOS standard-cell based design technique using Schmitt-trigger logic,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 47-60, January 2012.    M. Fojtik et al., “A millimeter-scale energy-autonomous sensor system with stacked battery and solar cells,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 801-13, 2013.    W. Lim, I. Lee, D. Sylvester, and D. Blaauw, “8.2 batteryless sub-nW cortex-M0+ processor with dynamic leakage-suppression logic,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 771 February 2015, pp. 1-3.    Analog low drop-out (LDO) regulators have shown rapid response times (e.g. TR=0.65 ns) and excellent steady-state performance. However, the input voltage, Vhi, is typically brought on-chip via either a high-efficiency switching dcdc converter or an external harvesting source, both with low-voltage subthreshold or near threshold outputs (e.g., 0.5 V). Analog LDOs have difficulty operating with the which such input voltages because of low-voltage headroom. Example analog LDOs are described in the following publications.    G. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, 1998.    K. N. Leung and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, October 2003.    M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low quiescent current low-dropout regulator with buffer impedance attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, August 2007.    M. Ho, K. N. Leung, and K.-L. Mak, “A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2466-2475, November 2010.    M. El-Nozahi, A. Amer, J. Tones, K. Entesari, and E. Sanchez-Sinencio, “High PSR low drop-out regulator with feed-forward ripple cancellation technique,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 565-577, March 2010.    J. Guo and K. N. Leung, “A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1896-1905, September 2010. 791    J. F. Bulzacchelli et al., “Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 863-874, April 2012.    Y. Lu, Y. Wang, Q. Pan, W.-H. Ki, and C. P. Yue, “A fully-integrated low-dropout regulator with full-spectrum power supply rejection,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 707-716, March 2015.
Digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. Typical Digital LDOs (DLDOs) replace a single saturated pMOS power transistor with an array of pMOS power transistors operating in the linear region, and can 33 operate down to 0.5 V since less headroom is required. Most switch-array-based DLDOs rely on an integral controller to linearly search (via a 1-bit ADC) for the pMOS array conductance that realizes the nearest output voltage, Vout, to the desired target, Vref. For an N-bit control, a linear search is used and can take up to 2N cycles. The following publication describe digital LDOs.    P. Hazucha et al., “High voltage tolerant linear regulator with fast digital control for biasing of integrated DC-DC converters,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 66-73, January 2007.    Y. Okuma et al., “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., September 2010, pp. 1-4.    Y. H. Lee et al., “A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm SoC for MIPS performance improvement,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1018-1030, April 2013.    S. Gangopadhyay, D. Somasekhar, J. W. Tschanz, and A. Raychowdhury, “A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2684-2693, November 2014.    S. Gangopadhyay, Y. Lee, S. B. Nasir, and A. Raychowdhury, “Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads,” in Proc. Design, Autom. Test Eur. Conf. Exhibit, March 2014, pp. 1-6.    W.-J. Tsou et al., “20.2 digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive volt-age scaling multicore processor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tech. Dig. Papers, February 2017, pp. 338-339.    M. Huang, Y. Lu, S. P. U, and R. P. Martins, “20.4 an output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tech. Dig. Papers, February 2017, pp. 342-343.    D. Kim, J. Kim, H. Ham, and M. Seok, “20.6 A 0.5V-VIN 1.44 mA-class event-driven digital LDO with a fully integrated 100 pF output capacitor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tech. Dig. Papers, February 2017, pp. 346-347.
More recent digital LDOs have proposed adding a proportional term via a multi-bit analog-to-digital converter ADC. However, the achievable response times are 44-4000 ns, which is insufficient for many digital loads. This approach with the added proportional term is discussed in the following publications.    D. Kim and M. Seok, “8.2 fully integrated low-drop-out regulator based on event-driven PI control,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tech. Dig. Papers, January 2016, pp. 148-149.    Y.-J. Lee et al., “A 200-mA digital low drop-out regulator with coarse-fine dual loop in mobile application processor,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 64-76, January 2017.
Digital LDOs often suffer from limited dynamic range over which the load is regulated and stable, and the DLDOs occupy a large active area due to barrel-shifter-based control. Typical prior DLDOs, like the one shown in FIG. 1, utilize a 2N unary-sized PMOS array driven through a 2N bit barrel-shifter that increments or decrements array conductance by a single (or a small number of) fingers per CLK cycle, resulting in a linear search over upwards of 2N cycles, which results in a 2N/N longer settling time than the proposed scheme. Typical LDOs occupy a large area with 2N D flip-flops (DFFs) in the area-dominant barrel-shifter. The barrel shifter accumulates 0's or 1's depending on the comparison: VOUT<VREF. As shown in FIG. 1B, the DLDO of FIG. 1B requires ˜2N×TCLK to reach a desired VREF.